1. Field of the Invention
The present invention relates to a silicon barrier capacitor device structure with high capacitance, In particular, the present invention relates to a silicon barrier capacitor device structure in semiconductor integrated circuits, to produce a capacitor with high capacitance, the process is compatible to silicon based process, so that without contaminating the silicon process by the dielectric layer of other high dielectric materials, then avoiding some problem of capacitor processing.
2. Description of the Related Art
The electronic industry has a conflict to repeat the necessary of a capacitor with high capacitance to satisfy the need of product by decreasing the thickness of the dielectric layer of a capacitor, and increasing the area of the capacitor. On the other hand, in order to achieve the requirement of thinner, lighter shorter and smaller, it is continuously decreasing the volume and area of the capacitor. To solve the above problem, the government, the scholar and the researcher, especially the semiconductor industry use their resources and manpower to develop topics related to capacitor, such as DRAM. As the increasing of the bit density, the capacitor may use trench capacitor or wing structures, even by using higher dielectric constant material such as BaTiO3 or other ferroelectrics materials to replace silicon dioxide (SiO2). For decreasing the thickness of dielectric of the capacitor, it cannot breakthrough because of the limits of processing technology and electric field breakdown. For increasing the area of the capacitor, it is conflict to shorter, lighter and smaller, especially when this is applied to the integrated circuit process, increasing the area of a capacitor will increase the cost of the integrated circuits, furthermore, the yield of production of integrated circuits will be low. For trench capacitor or stack (fin) capacitor, the difficulty of processing will decrease the yield and increase the cost of production. For replacing SiO2 by high dielectric materials, the process will not compatible with the mature silicon based process, this not only need to develop new ferroelectric materials, but also the ferroelectric material will become a serious contamination problem of the semiconductor silicon based process.
In the U.S. Pat. No. 2,152,0376 to Roap Rolland R; Butler charles E., constitutes a new area of barrier capacitor. Refer to FIG. 1, FIG. 1 is a prior art, by combining a layer of reduced ceramic BaTiO3 103 with low resistively and a layer of oxidized ceramic BaTiO3 102 with high resistively to form a barrier capacitor 100, then deposite a layer of conductive material 104 on the two sides of the dielectric layer to be the electrodes of the capacitor structure. By using the character of the high resistively of the grain boundary 106 and the low resistivity of the grain crystal 105, as an external voltage is applied to the two electrodes 104 and 101, the grain crystal almost without voltage drop due to its low resistivity character, However, the grain boundary 106 with its high resistivity characteristic that most of the voltage drop between the two electrode 104 and 101 will across the grain boundary 106. The equivalent capacitance will be:
                    C        =                              ɛ            r                    ⁢                      ɛ            0                    ⁢                      A                          d              c                                                          (        1        )            Where dc is the thickness of the dielectric between the two electrodes.                A is the area of the dielectric.        ∈r∈0 is the dielectric constant.The microstructure of this barrier layer capacitor 200 is shown in FIG. 2. The theoretic microstructure of the barrier layer capacitor is shown in FIG. 3.        
Refer to FIG. 2, the barrier layer dielectric between the upper electrode 204 and the lower electrode 203 is composed by grain crystal 202 and grain boundary 201. In FIG. 2, dc is the thickness of the dielectric between the upper electrode 204 and the lower electrode 203. The idealized structure is shown in FIG. 3, The barrier layer dielectric is idealized to n layers of grain crystal 302 with thickness of dG and grain boundary with thickness di.
Since the resistance of the grain crystal 202, 302 is much lower than the resistance of the grain boundary 201, 301, most of the voltage drop between electrodes 203, 204 or 303, 304 will appear in the grain boundary 201, 301. Equation (1) will become:
                    C        =                              ɛ            eff                    ⁢                      ɛ            0                    ⁢                      A                          nd              i                                                          (        2        )                            where n means that in the thickness of the dielectric dc between the two electrode 303, 304 has n dielectric grain crystal 302, that is:n=dc/(di+dg)  (3)        where d g is the average diameter of the grain crystal 302,                    d i is the average width of the grain boacndary 301.                        
Since d g>>d I, generally, d g˜103 d i or more, so that the capacitance will increase more than 1000 time as compare to that of the traditional capacitor. However, the dielectric loss of the capacitor made by this method is not small, the Formular for the dielectric loss is:
                              tan          ⁢                                          ⁢          δ                =                              1                          ω              ⁢                                                          ⁢              RC                                =                      1                          ωρ              ⁢                                                          ⁢              k              ⁢                                                          ⁢                              ɛ                0                                                                        (        4        )                                r        =                              dI            ×            ri                    +          rg                                    (        5        )                            where        r g is the resistance of the grain crystal 302,                    r i is the resistance of the grain boundary 301.                        
When it is applied to low frequency, the dielectric loss will be so high that it is difficult to accept it, unless the resistance of the grain boundary 301 is intensively made to be very high (otherwise Equation (2) would not true) so that we can obtain a barrier layer capacitor 200 or 300.